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White Electronic Designs
512K x 32 SSRAM / 1M x 64 SDRAM
FEATURES

Clock speeds: SSRAM: 100 MHz SDRAM: 100 MHz
WED9LAPC2C16V8BC
EXTERNAL MEMORY SOLUTION FOR LUCENT'S LUCTAPC640 ATM PORT CONTROLLER
DESCRIPTION
100% tested to timing requirements of LUCTAPC640's memory interface Packaging:
The WED9LAPC2C16V8BC is a 3.3V, 512K x 32 Synchronous Pipeline SRAM and a 1M x 64 Synchronous DRAM array packaged in a 21mm x 21mm 192 lead BGA. The WED9LAPC2C16V8BC provides the memory required for the CRAM (Control Memory) and VCRAM (Virtual Connection Memory) memory ports for Lucent's LUCTAPC640 ATM port controller. When used in conjunction with the WED9LAPC2B16P8BC, which provides memory for the BRAM (Buffer Memory) and PRAM (Pointer Memory) memory ports, the entire memory requirement of the LUCTAPC640 can be met using these 2 BGA devices. The WED9LAPC2C16V8BC is 100% tested to the timing requirements of the LUCTAPC640's memory interface timing for both Commercial and Industrial temperature ranges.
192 pin BGA, 21mm x 21mm
3.3V Operating supply voltage Direct control interface to both the CRAM and VCRAM ports on the LUCTAPC640 62% space savings vs. monolithic solution Reduced system inductance and capacitance
PIN CONFIGURATION PINOUT CRAM AND VCRAM MCM -- TOP VIEW
1 A B C D E F G H J K L M N P R T CADDR CWE# COE# VSS GCK VSS VCDATA_b VCDATA_b VCC VCDATA_b VCDATA_b VSS VCDATA_b VCDATA_b VCC VCDATA_b 2 CADDR CADDR CADDR CADDR VSS VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b 3 VCC CDATA CDATA CADDR NC VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VCDATA_b VSS 4 CDATA CDATA CDATA VCC VCC VCC VSS VSS VSS VCC VCC VCC VSS VCDATA_b VCDATA_b VCDATA_b VSS VCDATA_b VCBS VCDQM VSS VSS VCADDR8 VCCAS# VCC VCADDR0 VCADDR1 VCWE# VCC VCADDR2 VCADDR3 VCRAS# VCC VCADDR10 VCADDR4 VCADDR5 VSS VCADDR6 VCADDR7 VCADDR9/AP VSS VSS VCDATA_a VCC VSS VCDATA_a VCDATA_a VCDATA_a 5 CDATA CDATA CDATA VCC 6 VSS CDATA CDATA VCC 7 CDATA CDATA CDATA VSS 8 CDATA CDATA CDATA VSS 9 VCC CDATA CDATA VSS 10 CDATA CDATA CDATA VCC 11 CDATA CDATA CDATA VCC 12 VSS CDATA CDATA VCC 13 CDATA CDATA CDATA VSS VSS VCC VCC VSS VSS VSS VCC VCC VCC VCDATA_a VCDATA_a VCDATA_a 14 CDATA CDATA CDATA CADDR CADDR CADDR0 VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCC VCDATA_a VCDATA_a VSS 15 VCC CADDR CADDR CADDR CADDR CADDR1 VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a VCDATA_a 16 CADDR CADDR CADDR CADDR CADDR VSS VCDATA_a VCDATA_a VCC VCDATA_a VCDATA_a VSS VCDATA_a VCDATA_a VCC VCDATA_a
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 0 July 2000 Rev. Rev. #15168 ECO 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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WED9LAPC2C16V8BC
PIN CONFIGURATION (CONTINUED) PIN DESCRIPTION
Symbol CADDR CDATA CWE# COE# VCADDR VCDATA VCBS VCDQM VCRAS# VCCAS# VCWE# GCK VCC VSS Pin Name CRAM Address CRAM Data CRAM write enable CRAM output enable VCRAM address VCRAM data VCRAM bank select VCRAM DQM VCRAM row address strobe VCRAM column address strobe VCRAM write enable Global clock Power supply Ground Description Address pins for the SSRAM that serves as the control RAM (CRAM) Data I/O pins for the SSRAM control memory (CRAM) Write enable control for the SSRAM control memory (CRAM) Output enable control pin for the SSRAM control memory (CRAM) Address pins for the SDRAM memory that serves as the virtual connection memory (VCRAM) Data I/O pins for the SDRAM virtual connection memory (VCRAM) Bank address pin for the SDRAM virtual connection memory (VCRAM) DQM (data mask) pin for the SDRAM virtual conection memory (VCRAM) RAS# pin for the SDRAM virtual connection memory (VCRAM) CAS# pin for the SDRAM virtual connection memory (VCRAM) Write enable pin for the SDRAM virtual connection memory (VCRAM) Common clock pin for both the CRAM and VCRAM memory arrays Power supply pins Ground Pins
FIG. 1 BLOCK DIAGRAM 512K X 32 SSRAM / 1M X 64
CADDR0-18 GCLK CWE# COE# 512K x 32 SBSRAM ADDR0-18 CK GW# OE# DQ0-7 DQ8-15 DQ16-23 DQ24-31 CDATA0-31
VCADDR0-10 VCBS VCDQM
ADDR BA DQM0# DQM1# DQM2# DQM3# RAS# CAS# WE# CK
512K x 32 x 2 SDRAM
DQ0-15 VCDATA0-31 DQ16-31
VCRAS# VCCAS# VCWE#
VCDATA0-63
ADDR BA DQM0# DQM1# DQM2# DQM3# RAS# CAS# WE# CK
512K x 32 x 2 SDRAM
DQ0-15 VCDATA32-63 DQ16-31
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ABSOLUTE MAXIMUM RATINGS
Voltage on VCC Relative to VSS Vin (DQx) Storage Temperature (BGA) Junction Temperature Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55C to +125C +125C 50 mA
WED9LAPC2C16V8BC
RECOMMENDED DC OPERATING CONDITIONS
(0C TA 70C; VCC = 3.3V 5% unless otherwise noted)
Parameter Supply Voltage (1) Input High Voltage (1,2) Input Low Voltage (1,2) Input Leakage Current 0 - VIN - Vcc Output Leakage (Output Disabled) 0 - VIN - Vcc CRAM Output High (IOH = -4mA) (1) CRAM Output Low (IOL = 8mA) (1) VCRAM Output High (IOH = -2mA) (1) VCRAM Output Low (IOL = 2mA) (1) NOTES: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +6.0V for t tKC/2 Undershoot: VIL -2.0V for t tKC/2 Symbol VCC VIH VIL ILI ILO VOH VOL VOH VOL Min 3.135 2.0 -0.3 -10 -10 2.4 -- 2.4 -- Max 3.465 VCC +0.3 0.8 10 10 -- 0.4 -- 0.4 Units V V V A A V V V V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Description Operating Current Operating Current Operating Current Operating Current Conditions CRAM and VCRAM active CRAM active/VCRAM inactive CRAM inactive/VCRAM active CRAM inactive/VCRAM inactive Symbol ICC1 ICC2 ICC3 ICC4 Typ 400 350 270 150 Max 500 390 330 180 Units mA mA mA mA
BGA CAPACITANCE
Description Address Input Capacitance1 Input/Output Capacitance (DQ)1 Control Input Capacitance1 Clock Input Capacitance1 NOTE: 1. This parameter is sampled. Conditions TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz Symbol CI CO CA CCK Typ 5 8 5 4 Max 8 10 8 6 Units pF pF pF pF
SSRAM AC CHARACTERISTICS
Parameter Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z Output Enable to output valid Output Enable to output in Low-Z Output Enable to output in High-Z Address, Control, Data-in Setup Time to Clock Address, Control, Data-in Hold Time to Clock
July, 2000 Rev. 0 3
Symbol tKHKH tKLKH tKHKL tKHQV tKHQX tKQLZ tKQHZ tOELQV tOELZ tOEHZ tS tH
Min 7.5 3.0 3.0
Max
Units ns ns ns
4.2 1.5 1.5 1.5 0 3.5 1.5 0.5 3.5 4.2
ns ns ns ns ns ns ns ns ns
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Operation WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst Address Used External External External CWE# L H H
WED9LAPC2C16V8BC
SSRAM OPERATION TRUTH TABLE
COE# X L H CDATA D Q High-Z
NOTE: 1. X means "don't care", H means logic HIGH. L means logic LOW. 2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK. 3. For a write operation following a read operation, SSOE# must be HIGH before the input data required setup time plus High-Z time for SSOE# and staying HIGH thoughout the input data hold time. 4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
FIG. 2 SSRAM READ TIMING
tKHKH GCK tS CADDR
A1 A2 A3 A4 A5
tKHKL
tKLKH
tH COE# tOELQV CWE# tKQLZ CDATA tKHQX
Q(A1)
tOEHQZ
tKHQV
Q(A2) Q(A3) Q(A4) Q(A5)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIG. 3 SSRAM WRITE TIMING
WED9LAPC2C16V8BC
tKHKH
GCK
tKHKL
tKLKH
tS
CADDR
A1 A2 A3 A4 A5
tH
COE#
tS
CWE#
tH
tS
CDATA
D(A1)
tH
D(A2) D(A3) D(A4) D(A5)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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SDRAM AC CHARACTERISTICS
Parameter Clock Cycle Time1 Clock to valid Output delay1,2 Output Data Hold Time2 Clock HIGH Pulse Width3 Clock LOW Pulse Width3 Input Setup Time3 Input Hold Time3 CK to Output Low-Z2 CK to Output High-Z Row Active to Row Active Delay4 RAS# to CAS# Delay4 Row Precharge Time4 Row Active Time4 Row Cycle Time - Operation4 Row Cycle Time - Auto Refresh4,8 Last Data in to New Column Address Delay5 Last Data in to Row Precharge5 Last Data in to Burst Stop5 Column Address to Column Address Delay6 Number of Valid Output Data7 CL = 3 CL = 2 Symbol tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD Min 8 10 2.5 3 3 2 1 1
WED9LAPC2C16V8BC
Max 1000 1000 6
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CK CK ea ea
6 16 20 20 48 70 70 1 2 1 1
10,000
NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit.
2 1
CLOCK FREQUENCY AND LATENCY PARAMETERS
(Unit = number of clock) tRP 20ns 3 2 tRRD 16ns 2 2 Cycle Time 8.0ns 10.0ns CAS Latency 3 2 tRC 70ns 9 7 tRAS 48ns 6 5 tRCD 20ns 3 2 tCCD 10ns 1 1 tCDL 10ns 1 1 tRDL 10ns 2 2
REFRESH CYCLE PARAMETERS
Parameter Refresh Period1,2 Symbol tREF Min -- Max 64 Units ms
NOTES: 1. 1024 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FUNCTION Mode Register Set Auto Refresh (CBR) Precharge Single Bank Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Data Write/Output Disable Data Mask/Output Disable
NOTES: 1. 2. 3. 4.
WED9LAPC2C16V8BC
SDRAM COMMAND TRUTH TABLE
VCRAS# L L L L L H H H H H H X X VCCAS# L L H H H L L L L H H X X VCWE# L H L L H L L L H L H X X VCDQM# X X X X X X X X X X X L H VCBS X BA X BA BA BA BA BA X X X X VCADDR OP CODE X L H Row Address L H L H X X X X NOTES
2 2 2 2 2 2 3 4 4
All of the SDRAM operations are defined by states of VCWE#, VCRAS#, VCCAS#, and VCDQM# at the positive rising edge of the clock. Bank Select (VCBS), if VCBS = 0 then bank A is selected, if VCBS = 1 then bank B is selected. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. The VCDQM# has two functions for the data DQ Read and Write operations. During a Read cycle, when VCDQM# goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. VCDQM# also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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Command VCRAS# VCCAS# VCWE# L L L L L H L H L L H H H L L H L H H H L H H H L L L L L H L H L L H H H L L H L H H H L H H H L L L L L H L H L L H H H L L H L H H H L H H H L L L L L H L H L L H H H L L H L H H H L H H H L L L L L H L H L L H H H L L H L H H H L H H H VCBS VCADDR OP Code X X X X BA Row Address BA Column BA Column X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation
WED9LAPC2C16V8BC
SDRAM CURRENT STATE TRUTH TABLE
Current State Action Set the Mode Register Start Auto No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Notes 1 1
Idle
2 1 1
Row Active
3 1 4,5 4,5
Read
2 5,6 5,6
Write
2 5,6 5,6
Read with Auto Precharge
2 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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Command VCCAS# L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H VCWE# L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H VCBS X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X VCADDR OP Code X X Row Address Column Column X X OP Code X X Row Address Column Column X X OP Code X X Row Address Column Column X X OP Code X X Row Address Column Column X X OP Code X X Row Address Column Column X X
WED9LAPC2C16V8BC
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Current State VCRAS# L L L L Write with Auto Precharge H H H H L L L L Precharging H H H H L L L L Row Activating H H H H L L L L Write Recovering H H H H L L L Write Recovering L with Auto H Precharge H H H Action Description Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL Precharge ILLEGAL Bank Activate ILLEGAL Write ILLEGAL Read ILLEGAL Burst Termination ILLEGAL No Operation Continue the Burst Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL Precharge No Operation; Bank(s) idle after tRP Bank Activate ILLEGAL Write w/o Precharge ILLEGAL Read w/o Precharge ILLEGAL Burst Termination No Operation; Bank(s) idle after tRP No Operation No Operation; Bank(s) idle after tRP Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL Precharge ILLEGAL Bank Activate ILLEGAL Write ILLEGAL Read ILLEGAL Burst Termination No Operation; Row active after tRCD No Operation No Operation; Row active after tRCD Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL Precharge ILLEGAL Bank Activate ILLEGAL Write Start Write; Determine if Auto Precharge Read Start Read; Determine if Auto Precharge Burst Termination No Operation; Row active after tDPL No Operation No Operation; Row active after tDPL Mode Register Set ILLEGAL Auto orSelf Refresh ILLEGAL Precharge ILLEGAL Bank Activate ILLEGAL Write ILLEGAL Read ILLEGAL Burst Termination No Operation; Precharge after tDPL No Operation No Operation; Precharge after tDPL Notes
2 2
2 2 20
2 2 2 2
2 2 6 6
2 2 2,6 2,6
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Command VCCAS# L L H H L L H H L L H H L L H H VCWE# L H L H L H L H L H L H L H L H VCBS X X BA BA BA X X X X BA BA BA X X VCADDR OP Code X X Row Address Column Column X X OP Code X X Row Address Column Column X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation
WED9LAPC2C16V8BC
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Current State VCRAS# L L L L Refreshing H H H H L L L L Mode Register Accessing H H H H Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles Notes
Notes: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if VCBS selects this bank then the action is illegal. If VCBS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (tRAS) must be satisfied. 4. The VCRAS# to VCCAS# Delay (tRCD) must occur before the command is given. 5. Address VCADDR9/AP is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank-to-bank delay time (tRRD) is not satisfied.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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WED9LAPC2C16V8BC
FIG. 4 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @CAS LATENCY = 3, BURST LENGTH = 1
0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tCC tRCD
tCH
tCL tRAS tRCD tRP
tSS
VCRAS#
tSH
tSS
VCCAS#
tSH
tCCD
tSS
VCADDR
Ra
tSH
Ca
tSS
Cb
tSH
Cc Rb
VCBS
BS
BS
BS
BS
BS
BS
VCADDR9/AP
Ra
Rb
tRAC
VCDATA
tSAC
Qa
tSS
Db
tSH
Qc
tSLZ
VCWE#
tOH
tSS
tSH
tSS
VCDQM#
tSH
Row Active
Read
Write
Read Precharge
Row Active
DON' T CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIG. 5 SDRAM POWER UP SEQUENCE
0 GCK 1 2 3 4 5 6 7 8 9 10 11 12
WED9LAPC2C16V8BC
13
14
15
16
17
18
19
tRP
VCRAS#
tRFC
tRFC
VCCAS#
VCADDR
Key
RAa
VCBS
VCADDR9/AP
RAa
VCDATA
HIGH-Z
VCWE#
VCDQM#
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (A-Bank)
DON'T CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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0 GCK 1 2 3 4 5 6 7 8 9 10 11 12
WED9LAPC2C16V8BC
FIG. 6 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
13 14 15 16 17 18 19
tRCD
VCRAS#
tRC
Note 1
VCCAS#
VCADDR
Ra
Ca0
Rb
Cb0
VCBS
VCADDR9/AP
Ra
Rb
Note 3
tRAC
tSAC
Qa0
tOH
Qa1 Qa2
tSHZ
Qa3
Note 4 Db0 Db1 Db2 Db3
tRDL
CL = 2 VCDATA CL = 3
Note 3
tRAC
tSAC
tOH
Qa0 Qa1 Qa2
tSHZ
Qa3
Note 4 Db0 Db1 Db2 Db3
tRDL
VCWE#
VCDQM#
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
Notes: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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0 GCK 1 2 3 4 5 6 7 8 9 10 11 12
WED9LAPC2C16V8BC
FIG. 7 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
13 14 15 16 17 18 19
tRCD
VCRAS#
Note 2
VCCAS#
VCADDR
Ra
Ca0
Cb0
Cc0
Cd0
VCBS
VCADDR9/AP
Ra
tRDL
CL = 2 VCDATA CL = 3
Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Qa0 Qa1 Qb2 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1
tCDL
Dd0 Dd1
VCWE#
Note 1
Note 3
VCDQM#
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
Notes: 1. To write data before burst read ends. VCDQM# should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written. 3. VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
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0 GCK 1 2 3 4 5 6 7 8 9 10 11 12
WED9LAPC2C16V8BC
FIG. 8 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
13 14 15 16 17 18 19
VCRAS#
Note 1
VCCAS#
VCADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
VCBS
VCADDR9/AP
RAa
RBb
CL = 2 VCDATA CL = 3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
VCWE#
VCDQM#
Row Active (A-Bank)
Row Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
Note: 1. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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0 GCK 1 2 3 4 5 6 7 8 9 10 11 12
WED9LAPC2C16V8BC
FIG. 9 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
13 14 15 16 17 18 19
VCRAS#
Note 2
VCCAS#
VCADDR
RAa
CAa
RBb
CBb
CAc
CBd
VCBS
VCADDR9/AP
RAa
RBb
tCDL
VCDATA
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
tRDL
DBd1
VCWE#
Note 1
VCDQM#
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank)
Write (B-Bank)
Write (A-Bank)
Write (B-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. To interrupt burst write by Row precharge, VCDQM# should be asserted to mask invalid input data. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 16 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
0 GCK 1 2 3 4 5 6 7 8 9 10 11 12
WED9LAPC2C16V8BC
FIG. 10 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
13 14 15 16 17 18 19
VCRAS#
VCCAS#
VCADDR
RAa
CAa
RBb
CBb
RAc
CAc
VCBS
VCADDR9/AP
RAa
RBb
RAc
tCDL
CL = 2 VCDATA CL = 3
QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3
Note 1 QAc0 QAc1 QAc2
QAc0
QAc1
VCWE#
VCDQM#
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (A-Bank)
Read (A-Bank)
DON'T CARE
Note: 1. tCDL should be met to complete write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 17 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
0 GCK 1 2 3 4 5 6 7 8 9 10 11 12
WED9LAPC2C16V8BC
FIG. 11 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH = 4
13 14 15 16 17 18 19
VCRAS#
VCCAS#
VCADDR
Ra
Rb
Ca
Cb
VCBS
VCADDR9/AP
Ra
Rb
CL = 2 VCDATA CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
VCWE#
VCDQM#
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
DON'T CARE
Note: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 18 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
FIG. 12 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH = FULL PAGE
0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VCRAS#
VCCAS#
VCADDR
RAa
CAa
CAb
VCBS
VCADDR9/AP
RAa
Note 2
1 QAb0 QAb1 QAb2 QAb3 QAb4
1 QAb5
CL = 2 VCDATA CL = 3
QAa0
QAa1
QAa2
QAa3
QAa4
2 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4
2 QAb5
VCWE#
VCDQM#
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
Notes: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid VCDATAs after burst stop, it is the same as the case of VCRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each of them. But at burst write, burst stop and VCRAS# interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle." 3. Burst stop is valid at every burst length.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 19 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
FIG. 13 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @ BURST LENGTH = FULL PAGE
0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VCRAS#
VCCAS#
VCADDR
RAa
CAa
CAb
VCBS
VCADDR9/AP
RAa
tBDL
VCDATA
DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4
tRDL
Note 2 DAb5
VCWE#
VCDQM#
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
Notes: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. VCDQM# at write interrupt by precharge command is needed to prevent invalid write. VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 20 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
FIG. 14 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VCRAS#
Note 2
VCCAS#
VCADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
VCBS
VCADDR9/AP
RAa
RBb
RAc
CL = 2 VCDATA CL = 3
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
VCWE#
VCDQM#
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank)
Row Active (A-Bank) Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (Both Banks)
DON'T CARE
Notes: 1. BRSW modes enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at Write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 21 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 15 SDRAM MODE REGISTER SET CYCLE
0 GCK
Note 2
WED9LAPC2C16V8BC
1
2
3
4
5
6
VCRAS#
Note 1
VCCAS#
Note 3
VCADDR
Key
Ra
VCDATA
HI-Z
VCWE#
VCDQM#
MRS
New Command
DON'T CARE
*Both banks precharge should be completed before Mode Register Set cycle. NOTES: MODE REGISTER SET CYCLE 1. VCRAS#, VCCAS# & VCWE# activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new VCRAS# activation. 3. Please refer to Mode Register Set table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 22 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
REGISTER PROGRAMMED WITH MRS A10 TM A7 A6 A5 CAS Latency Burst Type A3 Type 0 Sequential 1 Interleave
WED9LAPC2C16V8BC
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Address Function BA0 RFU A9/AP RFU A8 W.B.L. A4 A3 BT A2 A1 Burst Length Burst Length A0 BT = 0 0 1 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Full Page A2
A10 0 0 1 1
Test Mode A7 Type 0 Mode Register Set 1 Reserved 0 Reserved 1 Reserved Write Burst Length A9 Length 0 Burst 1 Single Bit
A6 0 0 0 0 1 1 1 1
CAS Latency A5 A4 Latency 0 0 Reserved 0 1 Reserved 1 0 2 1 1 3 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved
Full Page Length: x32 (256)
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H",DQM = "H" and the other pins are NOP condition at the inputs. Maintain stable power, stable clock and NOP input condition for a minimum of 200s. Issue precharge commandes for all banks of the devices. Issue 2 or more auto-refresh commands. Issue a mode register set command to initialize the mode register. Sequence of 4 & 5 is regardless of the order.
2. 3. 4. 5. cf.)
The device is now ready for normal operation.
Note: 1. If A8 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) shuld stay "0" during MRS cycle.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 23 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE DESCRIPTION: 192 LEAD BGA 21MM X 21MM
d 0.10 PIN #A1 CORNER (4X) 21.00 0.10 8.00 REF A B 0.98 REF
A B OPTION PIN #A1 IDENTIFIER o1.00 0.10 INK OR LASER MARKING D E F G H J K L M N P R T C
WED9LAPC2C16V8BC
19.05 1.27 PIN #A1 CORNER
8.00 REF
21.00 0.10
1.27
TOP VIEW
0.70 0.05 0.36 0.04 0.60 0.10
2 0.75 0.05 0.30m C A B j 0.10m C
MAX 1.85
BOTTOM VIEW
NOTE 1. ALL DIMENSIONS AND TOLERANCE CONFORM TO ASME Y 14.5M-1994. f 0.10 d 0.15 C 3 SEATING PLANE 2. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C . C 3. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDIER BALLS. 4. THE SURFACE FINISH OF THE PACKAGE SHALL BE EDM CHARMILLE #24 - #27 5. UNLESS OTHERWISE SPECIFIED TOLERANCE : DECIMAL 0.05 ANGULAR 2
ORDERING INFORMATION
WED9LAPC2C16V8BC WED9LAPC2C16V8BI Commercial Temperature: Industrial Temperature: 0C to +70C -40C to +85C
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July, 2000 Rev. 0 24 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
0.98 REF
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
19.05

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